1. Field of the Invention
This invention is related to a substrate for mounting semiconductor elements (called semiconductor device substrate hereafter), a semiconductor device in which the semiconductor elements are mounted on the semiconductor device substrate and methods of fabricating them.
2. Related Art
There is growing needs for a smaller semiconductor device package with multiple terminal pins due to increases of an integration rate and an operation frequency in the recent semiconductor device. However, a package size of a conventional peripheral terminal type utilizing a leadframe has to be made larger if a number of the terminals should be increased further. One of countermeasures is to decrease a terminal pitch in the package. However, it is difficult to make the terminal pitch narrower than 0.4 mm.
To accommodate such increasing number of the terminals, an area array type package with its terminals disposing over a surface plane is introduced. The area array type package requires to have a wiring substrate for providing wiring from a pad of semiconductor chips to external connection terminals. The semiconductor chip may be mounted either at the upper surface or the lower surface of the wiring substrate when the external connection terminals are disposed at the lower surface of the wiring substrate. When the semiconductor chip is mounted on the upper surface of the wiring substrate, interlayer connections between the upper surface and the lower surface of the wiring substrate have to be provided. When the semiconductor chip is mounted on the lower surface of the wiring substrate, the interlayer connections will not be required. However, a hollow space has to be provided to absorb total thickness of the semiconductor chip and its sealing material when the semiconductor chip is mounted on the lower surface of the wiring substrate.
The hollow space is called a cavity, and a structure with the cavity at the lower surface of the wiring substrate is called a cavity down structure. Typically, the structure can be made by hollowing out a semiconductor chip substrate, or by making a hole through the semiconductor device substrate and adhering a base plate thereto. Wiring for a multiple layer structure is required when heights of semiconductor chip bonding portions and external connection terminals are changed because the wiring is also disposed on the same surface in this structure. That is, a wiring structure body in consideration of a three dimensional spatial relationships among the semiconductor chip mount portion, the inner bonding portion connected to mounted semiconductor chips and the external connection terminal portion in which external connection terminals are formed.
One of the area array type semiconductor package is Ball Grid Array (BGA) in which solder balls are used as external connection terminals. Cost of the BGA is higher than that of a semiconductor device fabricated with a conventional leadframe, and reduction of the cost is anticipated. The higher cost is due to a fact that a structure and fabricating process of the semiconductor device substrate are more complex than that of a substrate with the leadframe. Accordingly, it is anticipated the development of simpler structure and fabricating process of the semiconductor device substrate.
The wiring substrate used for the area array type semiconductor package is typically called an interposer. The interposer may be roughly classified into a film type and a rigid plate type. A number of the wiring layers can be either one, or two, or three and more layers. Generally, the fabricating cost is lower for a fewer number of the wiring layers.
In the interposer so called TAB (Tape Automated Bonding) or TCP (Tape Carrier Package) and their packaging technology, the center portion of the interposer is bored through to store the semiconductor chip. With the rigid plate, the center portion of the interposer is similarly bored through to hollow the semiconductor chip store portion out and adhere a metal plate as a base plate thereto, or the cavity portion is fabricated at the center area of the interposer. The wiring is disposed only in a flat plane portion, not inside the cavity portion.
Among those conventional technologies, the lowest cost is expected with the single layer wiring structure. If the wiring is disposed at least in both surfaces of the interposer, the semiconductor chip mount portion and the external connection terminals may be divided at the upper and the lower surfaces.
However, the semiconductor chip mount portion and the external connection terminals are disposed on the same surface of the interposer with the single layer wiring structure. In such a single layer wiring structure, it is required to have the cavity portion on the wiring surface with a depth at least comparable to a thickness of the chip so as to store the chip therein. A method of fabricating such a cavity portion has become an important subject.
Further, recently, smaller external connection terminals such as solder balls have been promoted and the reduction of its height when mounted and the realization of finer pitches for external connection terminals have been attempted. However, in order to obtain thinner and smaller semiconductor devices, the structure optimization is also an important issue for the structure such as the semiconductor chip mount portion and the wiring substrate in consideration of technical developments of those smaller external connection terminals.
The present invention is made by considering the above mentioned subjects. An object of the present invention is to provide a semiconductor device substrate for mounting a semiconductor chip(s) and other elements, a method of fabricating the semiconductor device substrate, a semiconductor device wherein a semiconductor chip(s) is mounted on the semiconductor device substrate, and a method of fabricating the semiconductor device, those of which enable to reduce the size, increase the reliability, reduce the cost, and make standardization of design and fabricating method easier.
Another object of the present invention is to provide a semiconductor device, a semiconductor device substrate therefor and methods of fabricating them, which allow reduction of the thickness and the size of the semiconductor device.
Still another object of the present invention is to provide a semiconductor device substrate having a cavity portion and a semiconductor device using the same, the cavity portion having a structure determined based on the size of external connection terminals to be used.
The above object of the present invention is accomplished by a semiconductor device substrate with a cavity portion, or a semiconductor device fabricated by mounting at least one semiconductor chip in the cavity portion and sealing with sealant, wherein said semiconductor device substrate comprises wiring disposed along a surface of the substrate and wall surfaces of the substrate in the cavity portion, the wiring comprises an external connection terminal portion for connecting to external connection terminals which are provided on the surface of the substrate at a side of the cavity portion being opened, an internal connection terminal portion for connecting to the mounted semiconductor chip, and a wiring portion disposed in between the external connection terminal portion and the internal connection terminal portion, the wiring portion is buried in a surface of the substrate and one of said wall surfaces of the substrate in the cavity portion and the internal connection terminal portion is disposed inside of the cavity portion.
For example, the wall surface of the substrate in the cavity portion may be extended toward the bottom surface of the cavity portion with a slant angle which is set within a predetermined angle range. Concretely, the slant angle may be within a range of 5-40xc2x0, and preferably within a range of 10-40xc2x0. In other words, the slant structure may be fabricated so as that a ratio L/G may be within ranges of 1.2 less than L/G less than 11, 1.2 less than L/G less than 5.7 respectively, where G is a height of the slant structure of the wall surface of the substrate in the cavity portion, and L is its horizontal dimension.
The cavity portion is, for example, formed by a press forming process utilizing a press pattern with a projected portion. The cavity portion may also be formed into a multiple step structure.
Alternatively, the cavity portion may be provided with a semiconductor chip mount portion for a mounting semiconductor chip, which is formed by hollowing the cavity portion out further. A depth of the semiconductor chip mount portion which has been hollowed out is preferably larger than a thickness of a semiconductor chip to be mounted therein.
Furthermore, a height difference of a ramp between the external connection terminal portion disposed on the substrate surface and the internal connection terminal portion disposed inside of the cavity portion may be preferably not less than 0.05 mm in the semiconductor device substrate and the semiconductor device according to the present invention.
The terminals of the semiconductor chip mounted inside of the cavity portion and the internal connection terminal portions are wire-bonded, or, directly connected by a face-down bonding.
Furthermore, the wiring in the semiconductor device substrate and the semiconductor device according to the present invention may be preferably disposed in an area of the wall surface which does not include any of corner sections of the cavity portion.
Furthermore, the cavity portion may be formed substantially at the center of the major surface plane of the substrate, and the semiconductor chip may be mounted inside of the cavity portion so as the semiconductor chip to be positioned substantially at the center of a dimension of the thickness of the semiconductor device substrate. Alternatively, the semiconductor chip may be offset-mounted in the cavity portion with an offset amount of not bigger than 30% of the substrate thickness from the center position of the substrate""s thickness along a direction of the thickness. The cavity portion may have a size large enough to mount a plurality of device elements on its bottom surface area, and may be provided with a plurality of wiring sets to the plurality of device elements, and a plurality of semiconductor chips and passive device elements may be mounted in the cavity portion.
Furthermore, the wiring in the semiconductor device substrate and the semiconductor device according to the present invention is preferably formed by utilizing a squeeze shapeable wiring construction body consisting of only metals, the squeeze shapeable wiring construction body having a multiple layer structure including at least the first metal layer for constructing the wiring and the second metal layer which functions as a carrier layer.
Furthermore, a depth of the cavity portion may be less than a thickness of the semiconductor chip to be mounted, and the cavity portion may be hollowed out at the bottom surface of the cavity portion from the center portion along a direction of a thickness of the semiconductor device substrate up to a depth within a range of 0.5-2.5 times a thickness of the semiconductor chip to be mounted. Alternatively, a depth of the cavity portion may be less than a thickness of the semiconductor chip to be mounted, and the cavity portion may be hollowed out at the bottom surface of the cavity portion, and the semiconductor device substrate may be further comprising a resin layer formed by hardening prepregs so as to have an exposed hollowed-out bottom surface at least consisting of nonwoven fabrics. In this case, a metal plate with a thickness of not less than 0.035 mm may be adhered to a reverse side of the resin layer wherein the cavity portion was formed, a depth of the cavity portion may be less than a thickness of the semiconductor chip to be mounted, and the bottom of the cavity portion may be hollowed out to expose the metal plate. Alternatively, a metal plate with a thickness of not less than 0.20 mm may be adhered to the reverse side of the resin layer wherein the cavity portion was formed, a depth of the cavity portion may be made to be less than a thickness of the semiconductor chip to be mounted, and the bottom of the cavity portion may be hollowed out into the metal plate as much as the hollowed out depth in the metal plate is not less than 0.05 mm.
Furthermore, the hollow-out process of the resin layer may be stopped before reaching the metal plate.
The above object of the present invention may be accomplished by a fabricating method of a semiconductor device substrate, comprising the steps of: pressing to adhere a squeeze shapeable wiring construction body to a resin substrate, the wiring construction body consisting of all metals and having a multiple layer structure comprising at least the first metal layer and the second metal layer which functions as a carrier layer; coincidentally shaping the resin substrate so as to form a cavity portion therein with its wall surfaces having inclination angles within a predetermined range; and removing the metal layers except the first layer; wherein the wiring, which is buried in the substrate surface and wall surface of the substrate in the cavity portion, is formed and disposed along the substrate surface and the wall surface of the substrate in the cavity portion; and the wiring comprising an external connection terminal portion for connecting to external connection terminals disposed on a surface of the substrate on a side of the cavity opening, an inner connection terminal portion for connecting to a semiconductor chip to be mounted, and a wiring portion in between the external connection terminal portion and the inner connection terminal portion.
A percentage elongation after fracture of the squeeze shapeable wiring construction body is preferred to be not less than 2%. A thickness of the carrier layer composing the squeeze shapeable wiring construction body is preferred to be within a range of 0.010-0.050 mm. A slant angle range of the wall surface of the substrate in the cavity portion is preferred to be from 5xc2x0 to 40xc2x0, and a depth of the cavity portion is preferred to be at least not less than 30% of a thickness of a semiconductor chip to be mounted.
The hollow-out process may be performed on the bottom surface of the cavity portion after the cavity portion is formed, and after the hollow-out process, other metal layers may be removed. Performing the hollow-out process while having the other metal layers enable to increase a process accuracy at hollowed out edges.
The above object of the present invention may be accomplished by a fabricating method of a semiconductor device substrate having at least one cavity portion for mounting at least one semiconductor chip and wiring, comprising the steps of: a step for making a depth of the cavity portion less than a thickness of a semiconductor chip to be mounted, and a step for hollowing out the cavity portion at the bottom surface, wherein the wiring to the semiconductor chip mounted is cut during the hollow-out process, and the cut edge portion of the wiring reaches a fringe portion of a cavity portion formed by the hollow-out process. Accordingly, a process accuracy at edges of the cavity portion may be increase.
According to the present invention, a fine pitch wiring corresponding to a connection pitch of the semiconductor chip may be disposed while forming the cavity portion which is capable of mounting the semiconductor chip, and is suitable for an area array type semiconductor package. The semiconductor package utilizing this technology is suitable for CSP (Chip Scale Package), FBGA (Fine Pitch Ball Grid Array), BGA (Ball Grid Array), LGA (Land Grid Array) or the like.
In order to accomplish the another objects, there is provided, according to one aspect of the present invention, a semiconductor device fabricated by forming at least one cavity portion on a semiconductor device substrate, mounting at least one semiconductor chip in the cavity portion, and sealing with sealant, wherein the semiconductor device substrate includes wiring disposed along surface of the semiconductor chip substrate and wall surfaces of the substrate in the cavity portion. The wiring includes an external connection portion for connecting to external connection terminals which are provided on the surface of the semiconductor device substrate at a side of the cavity portion""s opening, an internal connection portion for connecting to the mounted semiconductor chip, and a wiring portion disposed between the external connection portion and the internal connection portion. Further, a depth of the cavity portion may be determined in accordance with a predetermined instruction based on a height of the external connection terminals.
More specifically, the internal connection portion may be positioned inside of the cavity portion and a depth from the surface of the semiconductor device substrate to the position of the internal connection portion is preferably not less than (0.3-0.8xcex1) mm where a height of the external connection terminal is xcex1 (mm).
The cavity portion may be provided with a semiconductor chip mount portion for mounting a semiconductor chip, which is formed by further hollowing out the cavity portion. A depth of the semiconductor chip mount portion is preferably a value in a range of predetermined values, the range may be including a thickness of a semiconductor chip to be mounted therein.
Preferably, when the semiconductor device is mounted on a mother substrate, a space between the mother substrate and the surface of the semiconductor device substrate may be from 0.7xcex1 to xcex1 and a space between the mother substrate and the surface of the sealant may be not less than 0.1 mm.
Still further, a height xcex1 of the external connection terminal may be preferably a value in a range from 0.05 to 0.3 mm, and a distance from a pad side surface of the mounted semiconductor chip to the sealant surface is preferably in a range of 0.15 to 0.2 mm.
Also, in order to accomplish the another objects, there is provided, according to another aspect of the present invention, a fabricating method of a semiconductor device substrate including at least one cavity portion in which at least one semiconductor chip is mounted, includes the steps of, for the semiconductor device substrate, pressing to adhere a squeeze shapeable wiring construction body to a resin substrate, the wiring construction body having a multiple layer structure including at least the first metal layer which is used as a wiring portion and the second metal layer which functions as a carrier layer, while forming a cavity portion the resin substrate and removing the metal layers except the first layer. The wiring, which is buried in the resin substrate surface and wall surface of the cavity portion, is formed and disposed along the resin substrate surface and the wall surface of the cavity portion. The wiring includes an external connection portion for connecting to external connection terminals disposed on a surface of the resin substrate on a side of the cavity opening, an inner connection portion for connecting to a semiconductor chip to be mounted, and a wiring between the external connection portion and the inner connection portion. A depth of the cavity portion is determined based on a height of the external connection terminal.
Furthermore, the semiconductor devices and the substrates in accordance with various aspects of the present invention described above may further comprise metal layers or plates for heat dissipation.